1. Field
Exemplary embodiments of the present invention relate to a nonvolatile semiconductor device, and more particularly, to a circuit for controlling a global word line in a nonvolatile semiconductor device.
2. Description of the Related Art
A semiconductor memory device is classified as volatile memory and nonvolatile memory according to whether data is retained when power is not supplied. A nonvolatile memory such as a flash memory is capable of recording and deleting data freely and retaining stored data without the supply of power. Specifically, since a NAND flash memory has a high degree of integration, the NAND flash memory has been widely used in various application fields for high capacity data storage.
In such a nonvolatile memory, it is necessary to perform an electrical erase and reprogramming process with respect to a designated unit of memory cells in order to change previously programmed data, differently from a volatile memory such as a dynamic random access memory (DRAM). More specifically, in order to program data in a memory cell in an initialized state and then change the data, a designated number of memory cells including the selected memory cell may be reinitialized through an electrical erase operation and subsequently the selected memory cell may be reprogrammed with the changed content. In general, a unit of memory cells performing the electrical erase is called a block, and a unit of memory cells performing data record, or more specifically, program, is called a page. Here, the “page” indicates a set of memory cells connected to one word line, and one block includes a plurality of (for example, 64 or 128) pages.
FIG. 1A is a diagram illustrating a part of a memory cell array of an NAND flash memory device.
Referring to FIG. 1A, a cell array of the NAND flash memory includes a plurality of cell strings 100 and 110, and the cell string 100 includes a plurality of memory cells serially connected to one another between a drain select transistor 101 and a source select transistor 103, and the cell string 110 includes a plurality of memory cells serially connected to one another between a drain select transistor 111 and a source select transistor 113. The drain select transistors 101 and 111 and the source select transistors 103 and 113 are connected to a drain select line DSL and a source select line SSL, respectively, and the memory cells in the cell strings 100 and 110 are connected to one another through a plurality of word lines WL<0> to WL<n>. The cell strings 100 and 110 are selectively connected to bit lines BL through the drain select transistors 101 and 111, and are selectively connected to a common source line CSL, which is connected to a ground voltage terminal, through the source select transistors 103 and 113. The cell strings 100 and 110 connected to the bit lines BL are connected in parallel to the common source line CSL, thereby forming one memory cell block.
To perform program, read, and erase operations in a NAND flash memory device, a bias voltage suitable is applied for each operation to a selected word line. For example, in a program operation, a program voltage (for example, 10 V or more) is applied to a word line selected by an input row address, and a pass voltage (for example, 10 V or less) is applied to remaining word lines. Meanwhile, as the capacity and integration degree of a memory device are increased, to reduce a disturbance phenomenon to an adjacent word line or a bit line (or a memory cell connected to the bit line), pass voltages at different voltage levels are applied to word lines within a designated distance from the word line selected in the program operation. The application of the pass voltages will be called a “boosting option.”
FIG. 1B is a diagram illustrating voltages applied to the word lines of FIG. 1A in a program operation.
Referring to FIG. 1B, a program voltage VPGM is applied to a word line WL<A> selected by an input row address A in the program operation, and different voltages VBST1, VBST2 and VBST3 are applied to word lines WL<A+3> to WL<A+1> and WL<A−1> to WL<A−3> within a designated distance from the selected word line WL<A> according to the distance to the selected word line WL<A> because the above-mentioned boosting option is applied the word lines. On the other hand, a pass voltage VPASS is applied to remaining word lines WL<n> to WL<A+4> and WL<A−4> to WL<0>.
Since the number of word lines of a NAND flash memory may be 32 to 128 (gradually increased) per one block, and one NAND flash memory includes 1000 or more blocks, the total number of word lines is 32,000 or more at minimum. In order to select one of the 32,000 or more word lines and directly apply a bias voltage to the selected word line, switches corresponding to the total 32,000*(the number of voltage to be generated) are required, which makes the configuration of a chip difficult.
In order to solve such a problem, a global word line (GWL) is used. In a NAND flash memory, while one block is operating, other blocks do not operate. In this regard, a two-stage configuration scheme is used where a global word line is generated as a sample set of word lines provided in one block, a voltage used for each operation is first applied to the global word line, and subsequently transferred to word lines in each block.
FIG. 2 is a diagram illustrating a word line control circuit of an NAND flash memory device according to the conventional art, and FIGS. 3 and 4 are detailed diagrams illustrating the row selection unit 105 of FIG. 2.
Referring to FIGS. 2 to 4, the conventional NAND flash memory device includes global word lines GWL<0:127>, a voltage pump 101, a row decoder unit 103, a row selection unit 105, a block decoder unit 107, a block selection unit 109, and a cell array area 111. The cell array area 111 includes a plurality of memory blocks BLOCK_0 to BLOCK_n, and it is assumed that the number of word lines in one block is 128. Thus, the number of the global word lines GWL<0:127> is also 128.
The voltage pump 101 generates a plurality of voltages V<0:7> used for applying voltages at different levels to word lines in program and read operations and the like. It is assumed that the number of the different voltages generated by the voltage pump 101 is 8.
The row decoder unit 103 receives a row address RADD for each operation, and generates control signals SWCTRL3<0:127> for applying different voltages to a word line selected by the row address RADD, word lines employing the boosting operation, and remaining word lines.
Referring to FIG. 3, the selection unit 105 may include a plurality of switch units SW0 to SW127 for selecting one of the voltages V<0:7> generated by the voltage pump 101 and applying the selected voltage to the global word lines GWL<0> to GWL<127>. In detail, the switch units SW0 to SW127 select one of the eight voltages V<0> to V<7> in response to the control signals SWCTRL<0> to SWCTRL<127> generated by the row decoder unit 103 and apply the selected voltage to the global word lines GWL<0> to GWL<127>, which are connected to the switch units SW0 to SW127, respectively. Thus, each switch unit includes eight switches, and a control signal (for example, the control signal SWCTRL<0> input to the switch unit SW0) that controls each switch unit is represented by 3 bits or more.
The block decoder unit 107 receives a block address BLADD and generates block control signals BLCTRL<0:n> for selecting blocks corresponding to the block address BLADD, and the block selection unit 109 connects the blocks corresponding to the input block address BLADD to the global word lines GWL<0> to GWL<127> in response to the block control signals BLCTRL<0:n>. In this way, voltages applied to the global word lines GWL<0> to GWL<127> are transferred to word lines in the selected block.
However, referring to FIG. 4, one switch unit SW0 connected to one global word line GWL<0> includes eight switches that select one of the eight different voltages V<0> to V<7>. Therefore, the 128 switch units SW0 to SW127 connected to the 128 global word lines GWL<0:127> include 1024 (=128*8) switches, and control signals of 384 (=128*3) bits are implemented to control the switches. The number of the switches is increased as the number of word lines in one block is increased or the number of bias voltages is increased. Furthermore, if the number of the switches is increased, since the number of the control signals for controlling the switches is also increased, they occupy a large area in a memory device as the memory device is highly integrated with high capacity.